Staff Verification Engineer
Platform Recruitment is looking for a Staff Verification Engineer
Job description
My client is developing a new RISC-V product family. They have a fantastic technical pedigree; they invest heavily in verification methodology research and only hire the best.
They're looking for verification engineers at all levels of seniority.
Principal Verification Engineer
Responsibilities:
- Develop and execute verification plans in collaboration with design and systems teams.
- Create and maintain testbenches using SystemVerilog, UVM.
- Work closely with RTL designers to understand architectural intent and corner cases.
- Write and review functional coverage models to ensure complete design verification.
Requirements:
- Extensive experience with SystemVerilog and UVM.
- Understanding of good testbench design and theoretical.
- Good scripting in Python/C++ is desirable
Apply to learn more!
Extra information
- Status
- Open
- Education Level
- Secondary School
- Location
- Greater Bristol Area
- Type of Contract
- Full-time jobs
- Published at
- 09-02-2026
- Full UK/EU driving license preferred
- No
- Car Preferred
- No
- Must be eligible to work in the EU
- No
- Cover Letter Required
- No
- Languages
- English
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