Job description
Senior Design Verification Engineer (FPGA/ASIC)
My client, an HFT firm, is seeking a Senior Design Verification Engineer to work on high-performance FPGA and ASIC systems used in ultra-low-latency, real-time environments.
Key responsibilities:
- Develop testbenches, tests, and verification environments for FPGA/ASIC designs
- Create and maintain detailed verification plans
- Debug and root-cause complex RTL issues
- Collaborate closely with hardware designers on new and existing projects
- Manage test suites, coverage, and CI infrastructure
- Contribute to internal tools and open-source verification projects
Key requirements:
- 3+ years’ experience in FPGA or ASIC functional verification
- Strong SystemVerilog skills (UVM or similar frameworks)
- Experience with functional and code coverage
- Proficiency in Python; C++ a plus
- Comfortable working in a Linux environment
- Familiarity with Verilator and/or Cocotb is advantageous
- Degree in Electrical Engineering, Computer Science, or related field
Extra information
- Status
- Open
- Education Level
- Secondary School
- Location
- London Area
- Type of Contract
- Full-time jobs
- Published at
- 28-02-2026
- Profession type
- Accountancy
- Full UK/EU driving license preferred
- No
- Car Preferred
- No
- Must be eligible to work in the EU
- No
- Cover Letter Required
- No
- Languages
- English
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